Theoretical and practical knowledge in the field of memory architectures, memory circuits, modeling of electronic components and circuits, RTL (Verilog) coding, simulation, timing analysis and formal verification.

Minimum 5-10 years of experience in the field of circuit design, modeling and verification. Strong technical leadership skills. Good knowledge regarding CMOS technology, physical design, memory architectures and interactions of the various functional blocks. Team player. Excellent communication skills. Highly motivated.

The Engineer will provide functional models for Sidense OTP IP products for use in common circuit simulator tools. Produce and maintain functional models of the memory and power supply blocks, develop test benches, perform simulations. Work with design teams, internal and external, to trouble shoot simulation problems.