Code Storage
Application Summary
As the amount of software in embedded processor applications continues to increase, system developers are looking for new ways to store boot code and other software. Traditionally, many systems stored code in an external memory, often Flash or EEPROM, and downloaded it to the processor chip as needed. Due to the slow access times associated with external Flash memory, the code was downloaded to embedded SRAM on the processor chip.
The power required to access off-chip memory along with security concerns of storing valuable code in an external memory has driven designers to store code, and often a large amount of it, in OTP on the processor chip. The memory technology used for this storage must be high density, low cost, low power and very secure and reliable. In addition, embedded OTP technology should provide an easy path for converting programmable OTP into mask ROM when code is frozen to reduce chip production cost.
Because of its small footprint, designers can utilize a Sidense OTP macro in an eMTP (emulated Multi-Time Programmable) mode for applications that require reprogramming just a few times over the life of a product without adding significant die area. A typical approach for eMTP operation is to reserve additional, un-programmed OTP space for new code storage and allocate some additional storage for a tag to keep track of which memory segment is currently being used. The information in the tag area is used to calculate the address offset for the data. The amount of uncommitted OTP storage depends on the number of times you need to update the stored information.
OTP Requirements for Code Storage
- High density – may be up to several Mbits
- Secure storage
- Low power
- Easy conversion of all or part of a macro to ROM for fixed code segments
- Small bit-cell area
- No modifications from standard logic CMOS process
- Field-programmable
- Ability to update code using an eMTP (emulated multi-time programmable) operational mode
Sidense OTP Features and Benefits
- Density up to 512Kbits per macro (multiple macros can be used for higher memory capacity per chip). Supports large code footprints.
- Fast access times allow execution of code from OTP, without the need for caching in on-chip SRAM.
- Highly secure – virtually impossible to reverse engineer bit-cell states – to ensure integrity and prevent theft of valuable code IP
- ROM conversion with a single mask-layer change to reduce programming time
- Mask ROM and field-programmable OTP hybrid allows part of code to be fixed
- Flexible partitioning between field-programmable OTP and mask ROM – no pre-planning needed
- 1T bit cell results in the smallest embedded field-programmable OTP bit-cell area in the industry to minimize code storage footprint and support eMTP operation
- Runs in standard logic CMOS processes with no added masks or process steps, thus adding zero cost to the process flow
- Support for programming in-package to support software development concurrently with hardware development and to support customer-specific software.
Replacing External Code Storage
Designers can realize significant cost savings using a Sidense OTP macro compared to using external EEPROM or Flash (external or embedded) to store software. Code can be executed from OTP obviating the need for RAM to run code.
Memory Address Mapping Scheme for eMTP
This generic example shows a possible OTP memory address space map for eMTP operation. The eMTP initialization phase includes calculating and storing the eMTP address offset based on the information in the Memory Tracking Area (memory macro boot rows). All the memory access is then handled by a memory controller, which translates the external address into the OTP address space.
