Careers Mixed Signal Layout Designer

Mixed Signal Layout Designer

Position Summary

The Mixed Signal Layout Designer will be an integral part of Layout Design team producing memory IP that includes digital and analog layout cells. Work closely with Design Engineers to implement layout blocks from schematics.

 

Company Overview:

Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.


Responsibilities:

  • Creating and maintaining layout databases
  • Responsible for ensuring correct layout (LVS/DRC) and quality layout
  • Doing floor planning for custom layout blocks of various complexity
  • Building complex, hierarchical layout blocks
  • Reading and understanding complex topological design rule manuals
  • Ability to overcome day to day challenges regarding layout spacial problems, project related problems, run verification problems (DRC/LVS/ERC/ANT/DFM). All this while meeting time constraints related to overall project deadlines
  • Successful candidates will work closely within the team of Layout and Design Engineers, and consult with multiple Design Engineers through the design phases to successfully deliver layout blocks

Required Skills and Experience:

  • Minimum 5 years in Layout Design or related discipline
  • Applicants must have an engineering degree or diploma in Electrical / Computer Engineering Technology
  • Experience using Mentor, Cadence or similar layout edit tools
  • Candidates must be motivated to be self sufficient, and are also responsible for ensuring that their work is in line with overall goals of the department
  • Knowledge of CMOS semiconductor and deep sub-micron physics, and understanding of circuit principles as affected by layout such as speed, power, noise & area
  • Programming experience with AMPLE, PERL, TCL preferable but not necessary
  • Familiarity with database management systems for revision control
  • Excellent communication & documentation skills
  • Good team play

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