Company Overview
Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nmand is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.
Role Summary:
The Senior CAD Engineer will be responsible for the CAD environment supporting a design community developing OTP memory IP products for multiple foundries and advanced technologies using custom design flows, place and route, database and compiler technology. The successful candidate would be a hands-on individual who will focus on the architecture, development, automation and support of design flows using custom circuit design and layout, place & route, foundry design kit support, and the entire CAD environment.
Required Qualifications: