Careers Senior Product Engineer

Senior Product Engineer

Role Summary:
The Senior Product Engineer will be responsible for a group of OTP memory IP products designed into multiple foundries and advanced technologies, from product definition and planning through to production. Responsibilities will include assisting test engineers with ATE HW/SW debug, evaluation of OTP memory test chips, statistical analysis of characterization results to set datasheet and production test limits to meet targets, test report generation, and direct interaction and collaboration with design, marketing, test engineering and foundry partners.

Company Overview

Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.

 

Required Qualifications:

  • BS/MS Electrical Engineering
  • 15+ years of industry experience, with a minimum of 10 years of product engineering experience in memory products, preferably NVM IP
  • Knowledge of memory fault models and required test techniques for detection
  • Experience with creating comprehensive test plans for evaluation, characterization and qualification
  • Experience with reliability tests (HTSL, HTOL, TDDB) for memory devices
  • Experience with DOE and defining split lots and test conditions for characterization over PVT
  • Demonstrated statistical analysis and technical report writing skills; experience with semiconductor parametric analysis tools
  • Ability to interpret test results and drive design changes to improve product performance
  • Programming skills in at least one language – C, Perl, Python, VBA
  • Excellent analytical and problem solving skills with the ability to look beyond the obvious
  • A good team player with excellent communication and technical leadership skills

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