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Sidense Demonstrates Working One-Time Programmable (OTP) Bit Cells in TSMC 16nm FinFET Technology

Test chips show successful read and program capability with excellent programmed cell characteristics for 1T-Fuse™ cells implemented in FinFET architecture

Ottawa, Canada – (September 4, 2014) - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that it successfully demonstrated read and write capability for its 1T-OTP bit-cell architecture on test silicon fabricated in a 16nm CMOS FinFET process. 

Read more: Sidense Demonstrates Working One-Time Programmable (OTP) Bit Cells in TSMC 16nm FinFET Technology

Sidense SHF Embedded Memory Macros Target High-Performance and Low-Power Applications in TSMC 28nm Processes

1T-OTP macros, ideal for mobile computing and communications applications, meet all TSMC9000 Quality Management Program requirements for 28HPL, 28HPM and 28HPC Processes

Ottawa, Canada – (May 29, 2014) - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that the Company’s 1T-OTP macros for TSMC’s 28nm HPL, HPM and HPC processes have met all TSMC9000 Quality Management Program requirements. Applications for Sidense SHF memory IP include code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration. 

Read more: Sidense SHF Embedded Memory Macros Target High-Performance and Low-Power Applications in TSMC 28nm...

Sidense 1T-OTP NVM Qualified in Second-Generation TSMC 180nm BCD Process

1T-OTP meets all TSMC9000 requirements for TSMC’s 180nm BCD Gen 2 process

OTP macros fully qualified for -40ºC to 150°C read and field-programmable operations

Ottawa, Canada – (April 30, 2014) - Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that the Company's 1T-OTP macros for TSMC's 180nm BCD 1.8/5.0V Gen 2 process have met all TSMC9000 Assessment program requirements. Sidense OTP macros, at this process node, support applications such as automotive and industrial electronics that require reliable operation and long-life data retention in high-temperature environments. Customers are using Sidense Automotive Grade OTP in a wide range of devices, including power-management ICs, sensors and microcontrollers for applications in automotive, industrial, mobile and consumer devices and systems.

Read more: Sidense 1T-OTP NVM Qualified in Second-Generation TSMC 180nm BCD Process

Another Sidense Win against Kilopass in the U.S Court of Appeals for the Federal Circuit

Attorney fee issue sent back to district court to determine if Kilopass pursued baseless patent infringement claims against Sidense

Ottawa, Canada – January 8, 2014 – Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that a panel of judges in the United States Court of Appeals for the Federal Circuit instructed the District Court for the Northern District of California to reconsider its ruling denying Sidense an award of the attorney's fees it incurred in successfully defending the patent infringement lawsuit filed against it by Kilopass Technology Inc. Because this decision has liberalized the legal standard for recovery of attorney fees, it has received extensive attention in the media.

Read more: Another Sidense Win against Kilopass in the U.S Court of Appeals for the Federal Circuit

Sidense 1T-OTP Memory Macros meet JEDEC Accelerated Testing Qualifications at Two TSMC 28nm Process Nodes

SHF Memory IP targets advanced process node designs

Ottawa, Canada – December 26, 2013 – Sidense Corp., a leading developer of non-volatile memory OTP IP cores, today announced that its SHF Non-Volatile Memory (NVM) macros have met stringent JEDEC accelerated testing requirements for TSMC's 28HPM and 28HPL process nodes.

The 28nm HPM node addresses applications requiring high speed as well as low-leakage power and is suitable for many applications from networking and tablets to mobile consumer products. The 28nm HPL low-power node is best suited for cellular baseband, application processor, wireless connectivity, and programmable logic applications.

Read more: Sidense 1T-OTP Memory Macros meet JEDEC Accelerated Testing Qualifications at Two TSMC 28nm...

Sidense Enjoys Record Fiscal Year 2013

Revenues doubled over Fiscal Year 2012

Ottawa, Canada – November 26, 2013 – Sidense Corp.,a leading developer of non-volatile memory OTP IP cores, today announced that its fiscal year 2013, which ended September 30, 2013 (FY2013), was its best year yet for revenue. In addition, the fourth quarter of FY2013 established a new quarterly revenue record for Sidense.

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Sidense OTP Helps Novatek Provide Customers with Cost-Effective and Reliable Display Drivers

Sidense 1T-OTP macros chosen by Novatek for use in mobile display driver ICs

Ottawa, Canada – November 12, 2013 – Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) OTP IP cores, today announced that Novatek Microelectronics Corp. has selected Sidense's 1T-Fuse™-based 1T-OTP memory IP for its display driver ICs for flat-panel displays. Novatek's decision to use Sidense's high-voltage SLP NVM macros was based on several compelling features, including very low power consumption, high reliability and small OTP macro footprint.

Read more: Sidense OTP Helps Novatek Provide Customers with Cost-Effective and Reliable Display Drivers

Sidense Advanced Process Node 1T-OTP to be used in Sigma Designs DTV Products

SHF non-volatile memory macros selected for 40nm product implementation

Ottawa, Canada – October 29, 2013- Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) OTP IP cores, today announced that Sigma Designs®, a leading provider of System-on-Chip (SoC) solutions for converging multimedia delivery of home entertainment, home control, and connectivity, has selected Sidense 1T-Fuse™-based 1T-OTP memory IP for use in their next generation DTV and home entertainment product lines.

Read more: Sidense Advanced Process Node 1T-OTP to be used in Sigma Designs DTV Products

Sidense OTP Preferred by MV Silicon for their Audio Device ICs

  • Sidense 1T-OTP macros used for customer program storage in MP3 players and other audio equipment

Ottawa, Canada – September 9, 2013- Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) OTP IP cores, today announced that Mountain View Silicon Technology (MV Silicon), a supplier of ICs used in a broad range of audio applications, has chosen Sidense 1T-Fuse™-based 1T-OTP memory IP for use in its ICs for processing, conversion and amplification in audio devices. 

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Sidense OTP Helps Richtek Technology Give Customers Cost-Effective and Efficient Power Management Solutions

Sidense 1T-OTP chosen by Richtek for its Small Size, Low Cost and High Reliability

Ottawa, Canada – Aug 29, 2013- Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) OTP IP cores, today announced that Richtek Technology has selected Sidense 1T-Fuse™-based 1T-OTP memory IP for its Power Management IC (PMIC) products. The decision to use Sidense SLP NVM macros was based on several 1T-OTP features that help give Richtek a competitive edge over other PMIC providers.

Read more: Sidense OTP Helps Richtek Technology Give Customers Cost-Effective and Efficient Power Management...

Sidense Announces SHF 1T-OTP Non-Volatile Memory IP for Advanced Process Chip Designs

  • SHF 1T-OTP targeted for SoCs implemented in 40nm, 28nm, 20nm and smaller geometries.
  • Sidense 1T-OTP used in a wide range of leading semiconductor manufacturers' 40nm and 28nm designs

Ottawa, Canada – July 31, 2013- Sidense Corp., a leading developer of Logic Non-Volatile Memory (LNVM) OTP IP cores, today announced its SHF (Sidense Hiper Fuse) one-time programmable (OTP) memory for ICs developed in advanced processes at 40nm, 28nm, 20nm and smaller geometries. Sidense SHF 1T-OTP has already been qualified in 40nm processes in both G and LP variants, and is completing qualification in multiple 28nm processes with 20nm qualification to follow.

Read more: Sidense Announces SHF 1T-OTP Non-Volatile Memory IP for Advanced Process Chip Designs