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Sidense Qualifies 1T-Fuse™ in UMC's 130nm Process

Embedded non-volatile memory IP ideal for low cost, secure applications.
Toronto and Ottawa, Canada - June 11th, 2007 - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced it has qualified its logic non-volatile memory (NVM) intellectual property (IP) in UMC's 130nm standard logic CMOS process.

Read more: Sidense Qualifies 1T-Fuse™ in UMC's 130nm Process

Sidense Achieves Working Embedded OTP at 65nm

Embedded Non-Volatile Memory IP Ideal for High-Volume, Cost-Effective Solutions
Ottawa, Canada - Nov 12th, 2007 - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced it has successfully achieved functional embedded NVM at 65nm silicon and will complete full qualification in Q1 of 2008. The initial 65nm offering includes standard/general and low power/leakage processes.

Read more: Sidense Achieves Working Embedded OTP at 65nm

Sidense Broadens OTP Offering with Additional Process Nodes at SMIC

Customers Now Have Wider Access to Industry's Smallest Footprint, Lowest Power and Highest Performance OTP IP
Ottawa, Canada and Shanghai, China - Dec 17th, 2007 - Sidense, a leading developer of Logic Non-Volatile Memory (NVM) IP cores, today announced that its one-time programmable (OTP) technology is available on Semiconductor Manufacturing International Corporation's (SMIC) 180nm and 90nm processes.

Read more: Sidense Broadens OTP Offering with Additional Process Nodes at SMIC

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