Many high-volume applications are migrating to 65nm and smaller processes. One difficulty chip designers face at these advanced process nodes is finding scalable non-volatile storage solutions. Charge-storage NVM products suffer from data retention issues in standard-logic CMOS process nodes at 65nm and below. Sidense's patented anti-fuse technology does not suffer from these data retention problems and scales to geometries below 45nm.
"Many customers have expressed excitement about our technology, which provides them with a low-power, reliable, and cost-effective path to 65nm, 45nm and beyond," said Xerxes Wania, President and CEO of Sidense. "With our OTP memory IP, our customers can develop competitive products for a broad range of applications."
65nm applications are price sensitive and Sidense's patented 1T-Fuse™ provides the industry's smallest NVM bit cell, leading to highly cost-effective solutions. Additionally, the technology can be manufactured on a standard-logic CMOS process with no additional masks or process steps.
This latest product offering enhances Sidense's broad NVM product portfolio, which is currently available from 180nm to 65nm at leading foundries.
Sidense provides secure, dense and reliable non-volatile one-time programmable (OTP) memory IP for use in standard-logic CMOS processes, with no additional masks or process steps required. Sidense's patented one-transistor 1T-Fuse™ architecture is available from 180nm to 65nm at leading foundries. Ideal applications include analog trimming, code storage, encryption keys such as HDCP, RFID and Chip ID, and configurable processors and logic. For more information, visit www.sidense.com.
Cain Communications for Sidense