December 4th, 2006, Toronto, ON - Sidense Corporation announced today that Xerxes Wania, CEO of the company will be taking part in the IP/SOC 2006 (IP-Based SoC Design) conference December 6th and 7th in Grenoble, France.
Sidense Receives Funding from Tech Capital Partners
Memory IP solution provides increased density and security for consumer electronics applications
Ottawa and Waterloo, ON - September 22nd, 2006 - Tech Capital Partners, a venture capital firm investing in early-stage technology companies, today announced it has invested in Sidense, a developer of memory semiconductor intellectual property (MSIP) cores for the non-volatile memory (NVM) market. The funds will be used to expand marketing and sales efforts.
Sidense Announces Appointment of Steven Cliadakis as VP Worldwide Sales
September 14th, 2006, Ottawa and Toronto ON - Sidense, developer of non-volatile memory intellectual property (IP) cores for use in digital and analog devices, today announced that Steven Cliadakis has joined the company as Vice President of Worldwide Sales. Mr. Cliadakis will operate from Sidense's newly opened office in the Bay Area.
Sidense offers One Time Programmable (OTP) macro in UMCs 130nm Logic CMOS process
Ottawa, Canada - January 9th, 2006 - Sidense Corp. announced today that it has developed an embedded non-volatile memory (NVM) intellectual property (IP) core, targeted towards UMC's 130nm standard logic digital CMOS process.
Sidense to Deliver OTP Cores in UMC's 90nm and 65nm Process Nodes
OTP memory IP supplier to provide a path to cost reduction to SoC designers
OTTAWA, Canada, and HSINCHU, Taiwan - April 25th, 2006 - Sidense Corp., a provider of One-Time-Programmable (OTP) memory intellectual property (IP) and UMC (NYSE: UMC, TSE: 2303), a leading global semiconductor foundry, today announced that Sidense's 1T-fuse™ family of embedded OTP cores are slated to be silicon-verified in UMC 90nm and 65nm processes through UMC's IP Alliance Program and offered for use to system-on-chip (SoC) designers. The cores are scalable to UMC's CMOS processes without requiring additional mask or processing steps, providing users with shortened time-to-market and a path to cost reduction for their current and future designs.