Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company's innovative one-transistor 1T-Fuse™ architecture provides the industry's smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.
Sidense is headquartered in Ottawa, Ontario and services an expanding worldwide customer base.
As the Principal Engineer, Analog Design (NOC2147), you will provide technical (design) leadership to our OTP/IPS product family. Working with R&D and marketing, you will
- Define or maintain product specifications
- Lead the analog design activity across multiple process nodes
- Support Product Engineering during silicon evaluation phase to validate assertions from design phase and correlate expected and actual performance
- Improve and upgrade existing IPS designs based on silicon feedbackCollaborate with Memory architects to develop the optimal system level solutions
You will also apply your experience to help build our high-performance team, with the opportunity to guidance and mentoring of other engineers and support personnel.
This position is located in our Ottawa head office, 84 Hines Road, Suite 260, Ottawa Ontario Canada K2K 3G3.
- Extensive knowledge of analog circuits and design methodologies for the design of voltage references, regulators, charge pumps and power-up circuits, standard cells and I/O libraries
- Excellent communication skills to work with fellow architects and designers, and verification engineers
- Manufacturing knowledge and experience with silicon testing for design and specification correlation
- Understand and contribute to analog modeling and mixed mode simulations
- Hands-on experience leading the specification, development and delivery of Integrated Power Management products for memory systems through a gated flow process
- Experience interfacing with foundries, contractors and customers
- Knowledge of memory macrocell design, circuit and layout topologies for small and large arrays
- Demonstrated experience in writing clear, detailed design and circuit specifications
- Ability to conduct memory performance, power and yield estimates & trade-offs
- Experience with memory test chip, testing, characterization and reliability qualification
Compensation and Benefits
Compensation is commensurate with experience and education, expected to be between $96,000 and $120,000 per year. Company stock options may be considered for the successful candidate.
Benefits, including vacation, will be included in any offer. Reimbursement for relocation and short-term living allowances may be considered for the successful candidate.
Why work for us?
Sidense is an innovative company dedicated to becoming the leader in memory IP. This is why skilled, creative and dynamic professionals to join our team. At Sidense, you have the opportunity to work alongside technology thought leaders while directly contributing to the delivery of our world-class OTP IP.
To join the Sidense team:
Accommodation for applicants with disabilities is available upon request.