Senior Engineer,Test

The Opportunity

Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 40nm and is scalable to 28nm and below. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.

Sidense is headquartered in Ottawa, Ontario and services an expanding worldwide customer base.

Position Location: Ottawa


Using your background in semiconductors, you will develop and debug test programs for OTP memories and other IP blocks (IPS, PMC, DAP, BIST). You will be responsible for all aspects (both hardware and software) of evaluation, characterization and reliability testing. Some key responsibilities include:

  • Create and execute test specifications and plans for evaluation, characterization and qualification of Sidense IP on test chip vehicles.
  • Develop, debug, and maintain Credence PK2 tester programs/patterns for OTP macrocells and other IP blocks.
  • Develop programming algorithms and methodologies that optimize programming time and yield.
  • Develop test coverage for all critical device parameters and functions.


Required Qualifications:

  • Excellent analytical and problem solving skills with the ability to look beyond the obvious.
  • A good team player with excellent communication and technical leadership skills.
  • Experience in evaluating and characterizing semiconductor memory; knowledge of memory fault models and required test techniques for detection.
  • Experience creating comprehensive test plans for evaluation, characterization and qualification, analyzing test data and presenting results.
  • Experience in memory ATE programming (ex. Credence Kalos) and tester operation.
  • Experience with reliability tests (HTSL, HTOL, TDDB) for memory devices.
  • Able to review designs for testability, advise on DFT requirements.


Why work for us?

Sidense is an innovative company dedicated to becoming the leader in memory IP. This is why skilled, creative and dynamic professionals to join our team. At Sidense, you have the opportunity to work alongside technology thought leaders while directly contributing to the delivery of our world-class OTP IP.

To join the Sidense team:

Email your cover letter and resume in confidence to This email address is being protected from spambots. You need JavaScript enabled to view it.specifying the title of the position you are applying for in the subject line of your message. Please be sure to provide some insight into your initiative, skills and achievements, and how you plan to contribute toward the growth of our company.

Accommodation for applicants with disabilities is available upon request.

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