Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.
Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 16nm process technologies. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.
Sidense is headquartered in Ottawa, Ontario and services an expanding worldwide customer base.
As an Engineer, ASIC/RTL Design, you will be responsible for creation of new and improved digital designs for controllers, sequencers and protocol bridge IP. You would be expected to specify and plan your projects and ensure the highest quality through simulation and other verification techniques. You may also be involved in chip assembly tasks and in generation of verification models for integrated systems that contain your IP.
Applicants at both intermediate and senior level of experience will be considered.
Some of your key responsibilities will include:
- Develop and verify architectural/micro-architectural macro components
- Develop methods and procedures for automation of successive designs
- Perform simulations at the gate and block levels, performance analysis and verify functionality of assigned IPs with the goal of first silicon success across a broad range of technologies
- Provide guidance and mentoring of other engineers and support personnel
- Contribute to system level design and optimization
- Performing system level simulations to aid in the optimization of hard/soft IP boundaries
- Write generation and verification tools for your IP
- Computer Science or Engineering Bachelors degree (Masters preferred)
- 3-4 years experience in SOC, processor, or protocol-based design
- Knowledge of C/C++ or C#, Java and/or scripting languages
- Extensive Verilog design experience
- Knowledge of RTL and the synthesis flow including PnR. STA, and soft IP design flows
- Knowledge of AMBA and I2C is valuable
Why work for us?
Sidense is an innovative company dedicated to becoming the leader in memory IP. This is why skilled, creative and dynamic professionals want to join our team. At Sidense, you have the opportunity to work alongside technology thought leaders while directly contributing to the delivery of our world-class OTP IP.
To join the Sidense team:
Accommodation for applicants with disabilities is available upon request.