Company

Senior Designer, IC Layout

The Opportunity

Sidense provides secure, very dense and reliable non-volatile, one-time programmable (OTP) memory IP for use in standard-logic CMOS processes with no additional masks or process steps required and no impact on product yield. The Company’s innovative one-transistor 1T-Fuse™ architecture provides the industry’s smallest footprint, most reliable and lowest power Logic Non-Volatile Memory (NVM) IP solution. With over 70 patents granted or pending, Sidense OTP provides a field-programmable alternative solution to Flash, mask ROM and eFuse in many OTP and MTP applications.

Sidense OTP memory, embedded in over 100 customer designs, is available from 180nm down to 16nm process technologies. The IP is offered at and has been adopted by all top-tier semiconductor foundries and selected IDMs. Customers are using Sidense OTP for analog trimming, code storage, encryption keys such as HDCP, WHDI, RFID and Chip ID, medical, automotive, and configurable processors and logic.

Sidense is headquartered in Ottawa, Ontario and services an expanding worldwide customer base.

Description

In this role, the Senior Designer, IC Layout is responsible to translate an understanding of Sidense chip high-level design to floor planning of blocks. You will work collaboratively with IC Design to provide input and solutions to new product design, as well as provide technical guidance to other engineers working on related projects.

  • High-level floor planning (OTP, IPS, TC or other high level block)
  • Understanding and assembly of top-level design (OTP/IPS IP, test chip, PCM, other); some understanding of OTP memory architecture and tiled block requirements
  • Pad ring assembly, Sidense Pad modification
  • Setup and debug of DRC/LVS decks
  • Development of pitch constrained layouts

 

Required Qualifications

  • Motivated, capable of working as an individual contributor and as a team player
  • Able to lead a task force: guide, document, produce guidelines and methodologies
  • Experience using Mentor, Cadence or similar layout edit tools
  • Knowledge of CMOS semiconductor and deep sub-micron physics, and understanding of circuit principles as affected by layout such as speed, power, noise & area
  • Programming experience with AMPLE, skill, PERL, or TCL
  • Familiarity with database management systems for revision control
  • Knowledge of full custom to standard cell layout methodology
  • Experience specifically in development of tile-able memory macros
  • Prior experience with Mentor IC Design tools preferred

 

Why work for us?

Sidense is an innovative company dedicated to becoming the leader in memory IP. This is why skilled, creative and dynamic professionals want to join our team. At Sidense, you have the opportunity to work alongside technology thought leaders while directly contributing to the delivery of our world-class OTP IP.

To join the Sidense team:

Email your cover letter and resume in confidence to This email address is being protected from spambots. You need JavaScript enabled to view it. specifying the title of the position you are applying for in the subject line of your message. Please be sure to provide some insight into your initiative, skills and achievements, and how you plan to contribute toward the growth of our company.

Accommodation for applicants with disabilities is available upon request.

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