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Sidense SHF

Sidense SHF One-Time-Programmable (OTP) memory IP is based on a patented 1T-Fuse™ (anti-fuse) bit-cell. The 1T-Fuse bit-cell uses gate oxide breakdown as a robust, non-reversible programming mechanism. Optimized for high-performance and a wide range of bit densities, Sidense SHF macros are available for standard CMOS processes. There are no requirements for any additional masks or processing steps.

Sidense SHF memory IP is provided as a complete, non-volatile memory (NVM) subsystem providing interfaces and features to support a range of embedded SoC applications. The SHF module integrates the OTP memory and Integrated Power Supply (IPS) hard macro blocks along with program control, programming and test interface, error correction and Built-In Self Test (BIST) RTL. SHF applications include: code storage, ROM replacement, secure encryption key storage, configuration, fuse replacement, trimming and calibration.

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Standard Logic Processes 40nm IO voltages supported: 2.5V and 1.8V, 28nm, 20nm IO voltage: 1.8V. Cost-effective, highly reliable NVM for a wide range of uses including:
  • Code Storage, ROM Replacement
  • Encryption Key, COnfiguration, User Settings
  • Fuse Replacement (calibration, trim)
No additional masks or process steps required.
Small Footprints / High Densities Configurations from 1Kbit to 1.28Mbits per macro with I/O widths of 8,1 6, 24, 32 and 40 bits.
Flexible Metal Stacks OTP and power supply use few metal layers. Top used for power supply ports and are available for routing.
Integrated OTP Module Programming control and test interface, BIST, boot control, ECC and redundancy provided as RTL. Flexible architecture fits a wide range of system requirements.
Fast Read Speed Down to 20ns single (varies with configuration and process), faster redundant read modes. Execute code from OTP to reduce system cost, complexity and boot time.
Read Mode Options Single, Redundant, Double Redundant. Optimize for read performance and area.
Fast Program Time < 50µs / word with external VPP (varies with configuration and process). Multi-bit programming with charge pump. OTP can be easily converted to Mask ROM. Reduce test time and manufacturing cost.
Programmability On tester and in-field. Supports updates in-field and emulated Multi-Time Programming (eMTP). Optimize for programming performance and area.
Power Supplies Charge pump and regulator (IPS) supplied by on-chip VCC and VDD.
IPS configuration options to support various system and programming requirements including regulator only (using external VPP) and charge pump options to generate programming voltages in macro from VCC.
Operating Temp. -40°C to 125°C Read and Program Data retention exceeds 10 years at full duty cycle.
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SHF macros are ideally suited for a wide range of applications including:

  • Media and Application processors
  • Communications and Network security processors
  • Wireless chipsets
  • HDTV processors and interconnect ICs
  • PC Camera and Image sensors
  • PMICs
  • Peripheral controllers

Uses for SHF macros include:

Code Storage

Secure Encryption Keys

Analog Trimming and Calibration

Identification Tags


Please click here to request access to application briefs providing examples with area and power consumption.

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Memory bitcell Sidense 1T-Fuse
Density 1Kbit to 1.28Mbits (can use multiple macros for larger densities)
Process nodes 40nm to 20nm
Power Supply Integrated Power Supply with Charge Pump options (uses standard VCC and VDD)
Retention > 10 years
Key features
  • High Density
  • Small Area
  • Fast Read Access
  • Multiple Read Modes
  • Supports eMTP/Field Programming


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DocumentTo Access
SHF Product Brief Click to Download.
Datasheets NDA REQUIRED.
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