Designers face the challenge of creating secure, cost-effective, low power, and reliable designs. Sidense's embedded one-time programmable (OTP) technology, based on its patented single-transistor, split-channel 1T-Fuse^TM bit-cell architecture, enables designers to address this challenge. Sidense's single-transistor bit cell results in better yield, higher security, improved reliability and lower overall product cost.

SiPROM, SLP (Sidense Low Power) and ULP (Ultra Low Power) - Sidense's OTP IP product families - offer the industry's smallest footprints, low power, fast access times, and high reliability.

SiPROM

SiPROM macros provide a high-density replacement for masked ROM. Available in densities up to 512 Kbits, multiple macros may be combined to obtain larger memory capacity. SiPROM is ideal for high-capacity code storage and as a ROM replacement when higher security or field-programmability is required. SiPROM macros may be used in an emulated Multi-Time Programming (eMTP) mode and are easily converted into mask-programmable ROMs with a single mask change.

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SLP

SLP macros offer significant power and size reductions compared to SiPROM macros. They are available up to 256 Kbits and multiple macros may be combined to obtain larger memory capacity. SLP products target ultra low power and cost-sensitive applications such as implantable medical devices, mobile communications and RFID. SLP macros may be used in an emulated Multi-Time Programming (eMTP) mode and are easily converted into mask-programmable ROM with a single mask change.

ULP

ULP macros come in several configurations with densities up to 2 Kbits. ULP IP targets applications such as precision analog trimming and offers a field-programmable solution and much smaller area compared to eFuses. ULP provides a very low read voltage, built-in redundancy and data availability upon startup.

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Key features of Sidense products include:

• Use standard-logic CMOS fabrication processes
  • No additional masks or process steps required
  • Foundry Friendly - Portable across foundries and geometries to optimize vendor flexibility
• Highly reliable and secure data storage
  • No reverse engineering, unlike charge storage technologies
  • More reliable than alternative OTP solutions
  • Over 20 years retention time
  • Small bit cell dimensions allow an OTP macro to be used in an emulated Multi-Time Programmable (eMTP) mode at the system level
• Industry-leading specifications
  • Smallest footprint, as much as 50% less than alternatives
  • Low power, as much as 80% less than alternatives
  • Read access times down to 10 ns

For a complete list of available products please visit the Chip Estimate IP Catalog or send email to このメールアドレスはスパムボットから保護されています。観覧するにはJavaScriptを有効にして下さい .