Jim Lipman, Marketing Director, Sidense
Integrating third-party silicon memory intellectual property (IP) is not simple. While IP integrators are looking for turnkey IP solutions, problems caused by foundry differences at the same process node, difficulties associated with process scalability, and variability of both fabrication processes and analog circuits and sensors make "foundry-friendly" memory IP design for mixed-signal chips difficult.
This article discusses the requirements for analog trimming and sensor conditioning mechanisms, and describes the architecture and technology of a reliable, embedded non-volatile memory (NVM) that minimizes dependence on foundry-specific process steps. The field programmable memory and support circuitry can be implemented in standard logic CMOS processes, is inherently scalable to leading edge process nodes, and is very tolerant of process variability - a key consideration below 90-nanometers. When implemented in silicon, memory macros based on this technology provide an efficient mechanism for in situ digital calibration of analog sensors, such as those encountered in automotive and industrial applications, and for trimming analog circuitry to increase silicon yield.