NVM Insider Issue #11
| Index |
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| The NVM Insider, Issue 11 |
| Page 2 - Executive Opinion |
| Page 3 - Outside Thoughts |
| Page 4 - Tech Tidbits |
| Page 5 - Sidense Out and About |
| All Pages |
April 2011
A quarterly look at embedded NVM/OTP happenings
Proudly released in partnership with
Find our IP catalog on ChipEstimate.com.
Executive Opinion: A Message from the CEO
Xerxes Wania, President and CEO, Sidense
Since this newsletter marks the midpoint of Sidense's fiscal year, I thought I would summarize some of the milestones we've reached during the past six months.
Our bookings in the first two quarters of the fiscal year have surpassed bookings of fiscal 2010 and as you know, fiscal 2010 was a record year for Sidense. The growth in our bookings comes from old and new customers building SoCs that include wireless and wired standards such as ZigBee, UWB, HDMI, WHDMI and USB. We continue to grow our product offerings and see worldwide success in licensing our technology. On the manufacturing front, Sidense customers are now in production at 180, 130, 90 and 65nm nodes. We have also closed deals with customers at the leading-edge 40nm process node.
Outside Thoughts: Suitable IP is More than Just Function and Fit
Lonn Fiance, IP Business Manager, GLOBALFOUNDRIES
One of the key criteria in selecting a semiconductor IP component is its "suitability for the intended purpose." On the surface, this issue seems to be a straightforward question to be answered with a simple yes/no answer gleaned from a number on a datasheet or claims in a PowerPoint presentation. Considering this criterion more closely, however, reveals that it is a much more complex question with a more complex answer.
The obvious and industry-standard litmus test is silicon validation testing. This involves implementing the IP component in a selected process technology as a test chip and then validating the functionality and characterizing the electrical parameters of the manufactured part across a range of manufacturing process corners and operating conditions. Where appropriate, this may also include successfully executing a set of standardized tests to prove compliance with a given standardized interface (e.g. USB).
Tech Tidbits: 1T-OTP Test Features to Support In-Field Programmability
Craig Downing, Product Marketing Manager, Sidense
Sidense 1T-OTP is ideally suited to a broad range of applications and provides many benefits for many use cases, including security, reliability and cost-effective implementation. Its flexibility allows it to be used as a ROM or eFuse replacement supporting programming during manufacture and test. In addition many applications require programming of all or a part of the array in the field - for example supporting devices that allow firmware code revisions, security key updates or device configuration and adjustment.
Sidense Out and About
Press Releases
- Sidense Completes TSMC IP9000 Assessment for Non-Volatile Memory (NVM) Product Families (April 5, 2011)
- Sidense 1T-OTP Memory Available in ON Semiconductor 180 nm Process Technology (March 31, 2011)
- USPTO Validates Sidense's Non-infringement Position and Rejects Two Kilopass Patents (February 3, 2011)
- Sidense Granted all Claims by USPTO in Key Patent Dispute (January 26, 2011)
- Sidense Memory IP Qualified at Three GLOBALFOUNDRIES Processes (January 18, 2011)
Visit Sidense at the Upcoming Conferences and Tradeshows
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TSMC Technology Symposiums during the following dates:
Tuesday, April 5
San Jose McEnery Convention Center, 408 S. Almaden Blvd.,San Jose, CA 95110
Thursday, April 7
Four Seasons Hotel, 98 San Jacinto Blvd., Austin, TX 78701
Tuesday, April 12
Westin-Waltham Boston, 70 3rd Ave., Waltham, MA 02451
Tuesday, June 21
Amsterdam, The Netherlands
To schedule a meeting with Sidense at any of the TSMC U.S. Technology Symposiums, please contact Jim Lipman at This e-mail address is being protected from spambots. You need JavaScript enabled to view it . For scheduling a meeting at the TSMC Symposium in Amsterdam, please contact Wim van Seters at This e-mail address is being protected from spambots. You need JavaScript enabled to view it -
June 6-8, 2011
San Diego Convention Center, 111 W. Harbor Drive, San Diego, CA 92101
Sidense will be participating with some of their partners at DAC.- Speaking all three days at the ChipEstimate.com booth (IP Talks!), Monday at 3:30PM, Tuesday and Wednesday at 3:30PM
- Others to be announced shortly - check the Sidense website for updates
Sidense in the News
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Xerxes at the Common Platform Technology Forum - January 18, 2011
Click here to view the ChipEstimate.com interview with Sidense CEO and President Xerxes Wania
Find our IP catalog on ChipEstimate.com.