The NVM Insider, Issue 12 - Page 3 - Outside Thoughts

Outside Thoughts: Mobile Markets Bode Well for OTP Memory

By John Blyler, Editor-in-Chief, Chip Design Magazine

Analyst reports from IHS iSuppli suggest a strong market for NAND and DRAM memories, which will be good news to related non-volatile memory devices such as one-time programmable technologies.

If the latest reports are accurate, the mobile memory market will be worth $16.4 billion in 2011. IHS iSuppli researchers report that NAND memory will be the largest product segment this year, followed closely by mobile DRAM. NAND and mobile DRAM are used increasingly in high-end smart phones and tablets. In third place will be NOR memory devices, which are used mainly in lower-end mobile handsets in steadily decreasing amounts.

Before I go further, let's have a short refresher on the alphabet soup that is the world of memory acronyms. The two main types of memory used today are Random-Access Memory (RAM) and Read-Only Memory (ROM). RAM has very fast access times but burns a lot of power. ROM has much slower access rates but burns less power. The main difference between the two is that RAM needs a constant supply of power to retain its data. ROM retains its data even when power is removed. ROM is an example of non-volatile memory (NVM).

Both NAND and NOR devices are the two main types of nonvolatile ROM. NAND Flash is used in just about every consumer product you can imagine.

An interesting variation to standard types of embedded non-volatile memory is the use of One-Time Programmable (OTP) memory cores. Several fabless semiconductor intellectual property (IP) companies provide OTP memory, including Sidense, Kilopass and NSCore. Most of these companies use an anti-fuse memory approach that is implemented in standard-logic CMOS and requires no additional or post-processing mask steps. One advantage of Sidense's macrocell IP is that it uses very low power for memory applications in consumer markets.

One more memory refresher for those of us using RAM in our brains:  macrocells refer to hard IP blocks that must be placed manually in the SoC floorplan, whereas standard cells are typically provided by the semiconductor foundry.

One relatively easy way to improve memory performance and lower power consumption is to follow Moore's law, which leads automatically to reduced die size, faster performance and higher memory densities. A related benefit of Moore's law is a decrease in the voltage needed to power the transistors. Sidense has taken these benefits to heart by being the first to offer OTP antifuse-based memory cores at the leading-edge process node of 28nm (due in 2012) that also support 1.8V input/output interfaces.

Both low power and smaller die size are prerequisites for mobile applications, such as smart phones and tablets. Technology companies that meet these prerequisites should do well as the market for memory-related products continues to grow.

John Blyler is the Editor-in-Chief of Chip Design and Embedded Intel magazines and is the editorial director of Extension Media. John was the senior editor for Penton's Wireless Systems Design magazine and the IEEE I&M magazine. John has co-authored several books on technology (Wiley and Elsevier). He has over 23 years of systems engineering hardware-software experience in the electronics industry. John remains an affiliate professor in Systems Engineering at Portland State University. He holds a BS in Engineering Physics from Oregon State University, as well as a MSEE from California State University, Northridge. You can reach John at This e-mail address is being protected from spambots. You need JavaScript enabled to view it . For more information about Chip Design magazine, please visit http://chipdesignmag.com/