The NVM Insider, Issue 13

Index
The NVM Insider, Issue 13
Page 2 - Executive Opinion
Page 4 - Tech Tidbits
Page 5 - Sidense Out and About
All Pages

September 2011

A quarterly look at embedded NVM/OTP happenings

Xerxes Wania, President and CEO, Sidense

Executive Opinion: A Message From The CEO

Xerxes Wania, President and CEO, Sidense

Dear Customers, Partners and Suppliers,

During the past few weeks there has been a lot of confusing information regarding the Kilopass versus Sidense lawsuit. We would like to share our progress by pointing to certain facts that may help you understand the case better. Sidense believes it is winning its dispute with Kilopass, both in the Court and at the USPTO.

Read more

 

Kurt Shuler, VP of Marketing, Arteris

Outside Thoughts: Embedded Device Security and the Challenge of On-Chip Communication

By Kurt Shuler, VP of Marketing, Arteris

There isn't a day that goes by where we do not see a report about another mobile phone or other consumer electronics device being successfully hacked for nefarious purposes. The popularity of Apple's iPhone and phones based on Google's Android OS has made these devices an inviting target for credit card thieves, warez purveyors and even corporate spies. Our industry has responded with a layered defense consisting of both hardware and software. But new technology is enabling security schemes to be implemented at the system-on chip (SoC) interconnect level.

At the most base level, security starts when the phone or other electronic device is booted or turned on. One standard booting procedure used in most phones is called a "two stage" boot process. In this boot process, there is a first stage where the device boots by sending boot information from an internal read-only memory (ROM), non-volatile memory (NVM) or one-time programmable (OTP) memory to an internal static RAM (SRAM). This internal RAM is too small to hold all the required boot code, so its job is to cross load a larger set of boot code in a second stage. It is this second stage boot process that starts the device's operating system.

Read more

 

Tech Tidbits

Tech Tidbits: Sidense ULP 1T-OTP for Trimming and Calibrating Low-Power Devices

Craig Downing, Product Marketing Manager and Jim Lipman, Director of Marketing, Sidense

Analog ICs, sensors and mixed-signal SoCs that include analog circuitry need to meet precise specifications for analog signal behavior. To compensate for variations in chip processing and the effects of packaging, analog circuitry needs to be trimmed by adjusting part of the circuitry. Many devices such as silicon clocks, RFID chips and other devices used in applications such as mobile handsets also have very demanding requirements for low power consumption to maximize battery life or to operate within a very limited power budget.

Read more

 

Sidense Out and About

Press Releases

Articles

Visit Sidense at the Upcoming Conferences and Tradeshows

  • Open Innovation Platform (OIP) Ecosystem Forum Partner Pavilion on the following date:

    Tuesday, Oct. 18
    San Jose Convention Center, 150 West San Carlos St., San Jose, CA 95110

    Sidense exhibiting in Booth 215 from 8:00AM to 6:30PM
    Sidense is speaking at 2PM on &quote;An Essential 1T-OTP NVM Component for IC Design&quote;

    To schedule a meeting at the OIP Ecosystem Forum in San Jose, please contact Jim Lipman at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
  • Technology Symposium - Yokohama, Japan on the following date:

    Monday, November 28
    Pan Pacific Yokohama Bay Hotel Tokyu, 2-3-7, Minato Mirai, Nishi-ku, Yokohama, Kanagawa, Japan 220-8543

    Sidense exhibiting from 9AM to 5:30PM

    To schedule a meeting at the TSMC Technology Symposium in Yokohama, please contact Kazuaki Okawa at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Find our IP catalog on ChipEstimate.com.


Xerxes Wania, President and CEO, Sidense

Executive Opinion: A Message From The CEO

Xerxes Wania, President and CEO, Sidense

Dear Customers, Partners and Suppliers,

During the past few weeks there has been a lot of confusing information regarding the Kilopass versus Sidense lawsuit. We would like to share our progress by pointing to certain facts that may help you understand the case better. Sidense believes it is winning its dispute with Kilopass, both in the Court and at the USPTO.

  • Sidense is winning the USPTO proceedings with regard to its '855 patent, since the USPTO examiner has validated all of the '855 patent claims, granted patentability of six new claims, and rejected Kilopass' appeal arguments.
  • Sidense is winning USPTO proceedings challenging the 3 Kilopass patents being asserted in court (the '757, '540 and '751 patents), since the USPTO examiner has, so far, rejected all claims of the '757 and '540 patents as invalid.The USPTO upheld the claims of only the '751 patent which is going through an appeal process.
  • Sidense won a motion to dismiss one of 4 Kilopass business tort claims asserted against Sidense in Court.
  • Sidense has significantly undermined the remaining 3 Kilopass business tort claims by persuading the USPTO examiner that Sidense's '855 1T patent claims are valid over the Kilopass 1T patent claims, since those claims depend, amongst other things, on proof that Sidense does not own 1T patents.
  • Sidense has significantly undermined Kilopass' patent infringement claims by persuading the USPTO examiner that Kilopass' patents do not invalidate Sidense's 1T patents, which cover the 1T products Kilopass is accusing Sidense of having infringed.
  • Sidense appears to have fatally undermined Kilopass' patent infringement claims by persuading the Court to adopt two (effectively three) of its proposed claim term definitions and adopt independent claim term definitions for all but one of Kilopass' proposed claim term definitions.
  • Kilopass appears to agree that the Court's definitions have fatally undermined Kilopass' infringement case since, two days after the Court's claim construction ruling, Kilopass requested a five month delay in the trial date.
  • At the request of Sidense's new investors, after Kilopass first asserted patent infringement many years ago a respected U.S. law firm evaluated Kilopass' claims, concluded that there was no infringement and gave Sidense a Freedom To Operate opinion letter, which Sidense will be able to rely upon in court.
  • Similarly, within the past year, several Sidense customers and investors have conducted due diligence by having their own independent patent attorneys analyze Kilopass' infringement claims and, following those analyses, continued to do business with Sidense.

We value your business and are looking forward to put these legal issues behind us. If you have any questions, please do not hesitate to contact me.

Xerxes Wania
President and CEO

 

 

Kurt Shuler, VP of Marketing, Arteris

Outside Thoughts: Embedded Device Security and the Challenge of On-Chip Communication

By Kurt Shuler, VP of Marketing, Arteris

There isn't a day that goes by where we do not see a report about another mobile phone or other consumer electronics device being successfully hacked for nefarious purposes. The popularity of Apple's iPhone and phones based on Google's Android OS has made these devices an inviting target for credit card thieves, warez purveyors and even corporate spies. Our industry has responded with a layered defense consisting of both hardware and software. But new technology is enabling security schemes to be implemented at the system-on chip (SoC) interconnect level.

At the most base level, security starts when the phone or other electronic device is booted or turned on. One standard booting procedure used in most phones is called a "two stage" boot process. In this boot process, there is a first stage where the device boots by sending boot information from an internal read-only memory (ROM), non-volatile memory (NVM) or one-time programmable (OTP) memory to an internal static RAM (SRAM). This internal RAM is too small to hold all the required boot code, so its job is to cross load a larger set of boot code in a second stage. It is this second stage boot process that starts the device's operating system.

To ensure non-secure code is not loaded into the device during the boot phase, silicon vendors, device vendors and software vendors establish a chain of trust for their various ingredients. This chain of trust is enforced and validated through cryptographic protocols and means such as public key infrastructure (PKI). Because the hardware SoC is the only part of the system that can't be easily modified or reprogrammed, it is the root of trust for the system's cryptographic infrastructure, with individual device keys being stored in OTP or other memory. In the case of mobile phones, device-specific identifiers such as the International Mobile Equipment Identity (IMEI) can be stored in this memory.

At the user level, device and OS vendors respond to security threats by providing updates to operating system and anti-virus software. These updates are made available once a threat to the device has been diagnosed and fixes have been made in the software to stop it. In addition to being reactive, another drawback of this approach is that the software becomes increasingly complex as it is modified to address increasing numbers of threats.

New interconnect IP technology now allows another layer of security to be implemented in hardware at the SoC interconnect level, protecting all traffic on the chip whenever it is running. The core of this technology is based on the concept of a firewall. A firewall permits or denies transmission of on-chip traffic based on a set of rules. In the case of a network on chip interconnect, communications packets traveling from initiators (like CPUs) to targets (like memory) are checked against a set of rules to determine if they should be allowed to pass or marked invalid.

Firewalls are cascaded within the interconnect, allowing the SoC designer to architect a security scheme that will allow some use models but will invalidate others. For example, an interconnect-based security scheme could stop a non-secure Java application from accessing secure communication of credit card information from a trusted RAM.

This is a very simple example. Real-world implementations take into account the phone's existing use case and data traffic profiles before allowing suspect data to pass. Furthermore, if desired, trusted software can be permitted to program these firewalls during runtime to adapt to new restricted or permissible use cases.

Hardware security implemented within an SoC's network-on-chip interconnect allows designers to add another layer of protection that can be made to be nearly impossible to hack or work around. What can be done with this technology is limited only by the imagination of the SoC architect and the schedule time allotted to design the SoC.

Kurt Shuler Bio

Kurt Shuler is the marketing director at Arteris.

He has held senior roles at Intel, Texas Instruments, ARC International and two startups, Virtio and Tenison. Before working in high technology, Kurt flew as an air commando in the U.S. Air Force Special Operations Forces.

Kurt earned a B.S. in Aeronautical Engineering from the U.S. Air Force Academy and an MBA from the MIT Sloan School of Management.

You can reach Kurt at This e-mail address is being protected from spambots. You need JavaScript enabled to view it . For more information about Arteris, please visit http://www.arteris.com/

 


Tech Tidbits

Tech Tidbits: Sidense ULP 1T-OTP for Trimming and Calibrating Low-Power Devices

Craig Downing, Product Marketing Manager and Jim Lipman, Director of Marketing, Sidense

Analog ICs, sensors and mixed-signal SoCs that include analog circuitry need to meet precise specifications for analog signal behavior. To compensate for variations in chip processing and the effects of packaging, analog circuitry needs to be trimmed by adjusting part of the circuitry. Many devices such as silicon clocks, RFID chips and other devices used in applications such as mobile handsets also have very demanding requirements for low power consumption to maximize battery life or to operate within a very limited power budget.

The traditional method of implementing a trimming circuit uses metal or poly fuses (eFuses). For example, the eFuses may be connected to an array of resistors of varying values so they can be blown to adjust the resistance in a particular part of an analog circuit. This is similar to trimming a discrete circuit using a potentiometer. The problem with using eFuses for this purpose is that the blowing current required is high, which adds additional design challenges, particularly for low-power devices, and could potentially affect chip yield. Using eFuses also makes it difficult to trim in the field after manufacturing.

A better solution is to use OTP memory bit settings for trimming and calibration functions. Sidense 1T-OTP macros, with their small size, low power consumption, high reliability, and field programmability, simplify trim and calibrate operations without adding any processing cost to chip fabrication.

The field programmability of 1T-OTP enables other applications in addition to trimming, such as setting device parameters for different customer requirements. For example, a clock chip can use 1T-OTP to set a trimming circuit to cover a wide range of timing specifications after packaging or in a customer's system.

For very low-power devices, Sidense ULP 1T-OTP macros are an ideal solution for trimming and calibration. To enable low voltage operation, ULP macros use a differential-redundant read mode. This mode widens the operating margins so that read operations function reliably with a 1.5V supply. The ULP design also includes features to allow fast start-up read of data bits, then to power down the memory once the data has been latched in the macro. In this mode the macros use a very low supply voltage for standby operation. ULP macros support data bus widths up to 128 bits so that just one read operation at power-up can latch up to 16 bytes of data.

The following figure shows a Sidense 128-bit ULP macro used for setting the frequency of a silicon clock. The device can be trimmed during manufacture and test or after packaging to configure the device for a particular requirement. The power-up read operation supported by the ULP macro enables the device to quickly load settings and then put the OTP into a very low power standby mode, making it ideal for applications where low power consumption is critical.

techtidbit.png

Optional Integrated Power Supply macros are available to supply the programming voltage on-chip, otherwise an external programming voltage can be used. ULP macros are available for 180nm standard logic processes in various off-the-shelf configurations from 16 bits up to 2 Kbits.

Click here for more information about Sidense ULP macros and to download a ULP Product Brief.


Sidense Out and About

Press Releases

Articles

Visit Sidense at the Upcoming Conferences and Tradeshows

  • Open Innovation Platform (OIP) Ecosystem Forum Partner Pavilion on the following date:

    Tuesday, Oct. 18
    San Jose Convention Center, 150 West San Carlos St., San Jose, CA 95110

    Sidense exhibiting in Booth 215 from 8:00AM to 6:30PM
    Sidense is speaking at 2PM on &quote;An Essential 1T-OTP NVM Component for IC Design&quote;

    To schedule a meeting at the OIP Ecosystem Forum in San Jose, please contact Jim Lipman at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .
  • Technology Symposium - Yokohama, Japan on the following date:

    Monday, November 28
    Pan Pacific Yokohama Bay Hotel Tokyu, 2-3-7, Minato Mirai, Nishi-ku, Yokohama, Kanagawa, Japan 220-8543

    Sidense exhibiting from 9AM to 5:30PM

    To schedule a meeting at the TSMC Technology Symposium in Yokohama, please contact Kazuaki Okawa at This e-mail address is being protected from spambots. You need JavaScript enabled to view it .

Find our IP catalog on ChipEstimate.com.

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