|The NVM Insider, Issue 3|
|Page 2 - Executive Opinion|
|Page 3 - Outside Thoughts|
|Page 4 - NVM on the Mind|
The traditional SoC has long viewed the agility of its FPGA neighbor with envy, even as the FPGA has sought the low unit cost of an SoC. As they say, the grass is always greener on the other side. While structured ASICs have labored to keep one foot in the hardwired and programmable ponds, respectively, these vendors have primarily succeeded in adding an unacceptable delay in the path from flexibility during prototyping to low cost in volume production. New Platform Oriented Architecture (POA) based SoC devices are now enjoying the greater flexibility long associated with FPGA devices while maintaining their low unit costs.
Evidence of this trend is popping up all over as firmware located in embedded ROM consumes ever higher percentages of any given device’s content. Most notably, the availability of high-density non-volatile memory (NVM) makes it possible to store hardware configuration information on-chip. This enables the permanent storing of information for embedded controller configuration, firmware parameters, device security, address and data buses, I/O devices, and standard interface options, as well as tuning and/or trim information for analog features. This increased flexibility gives rise to POA design approaches used to address a range of requirements typically fulfilled by a semiconductor product series or chipset.
So, what does the prospect of design virtualization mean? Engineers are continuing to find new ways of doing fewer design starts each year by enabling more than one virtual (logical) design per physical device design. As with most evolutionary steps in hardware design, the trend toward POA architectures is driven by simple economics and the need for a competitive advantage in a difficult market. One physical design that supports a chip product series translates into reduced development costs including design, mask, debug, verification, and test costs for what would have been a multiple chipset program. From an operations viewpoint, it means one physical SKU (stock keeping unit) may support multiple virtual device SKUs through the process of soft SKU’ing. A single die SKU means more accurate forecasts, reduced inventory, reduced obsolescence, shorter lead times, and reduced price erosion. These are all strategic to manufacturing and a chip company’s bottom line.
An FPGA device’s intellectual property (IP) is contained in its configuration information. Similarly, a POA SoC device places more of its IP in configuration information stored in embedded NVM. It is imperative that this IP be protected physically within the device and during the manufacturing process in order to protect the product design IP, premium system features, hardware security, the product’s price, and the manufacturer’s brand. This avoids the mismarking of the manufacturer’s products, counterfeiting, and reverse-engineering by prospective competitors. All together, increased use of embedded NVM enhances the prospect for higher margins during a tough year in the chip industry and holds promise for a much brighter future!