The NVM Insider, Issue 5 - Page 2 - Executive Opinion

Executive Opinion: The Promise of NVM

Xerxes Wania, President & CEO, Sidense Corp.

If you are a chip designer looking to embed non-volatile memory on your design, there are plenty of technologies from which to choose, both one-time programmable (OTP) and multiple-time programmable (MTP). The decision of which one(s) to choose for your chip depends on many technology and business parameters, including speed, density, power, cost, scalability to new processes and portability to different foundries, just to name a few. With these constraints in mind, many of you have already seen some of the problems in using traditional embedded non-volatile memories – mask ROM, eFuse and Flash.

Each of these technologies has one or more limitations for evolving or upgraded chip designs:

• Mask ROM – Programming is done during wafer processing and is not field-programmable. Mask ROM is unable to support cost-effective, fast time-to-market configurable designs.
• eFuse – Large bit-cell area and limited in density to a few Kbits at most. Also not easily field-programmable.
• Flash – Poor process scalability and expensive to embed in a standard-logic CMOS process. Additional processing for embedded Flash may compromise the performance of high-speed logic.

These limitations, which have been helping to drive development of new types of NVM memories over the past several years, were frequently brought up at the recent Flash Memory Summit in Santa Clara, California, particularly during a well-attended session on Life Beyond Flash: New Non-Volatile Memory. Several evolving and one existing technology were discussed:

• MRAM, which uses a spin-polarized current to switch the magnetization of a bit-cell storage layer;
• CMOx™, which uses a multi-layer cross-point structure to move bit-cell charge; and,
• a switching memristor, a two-terminal switching device.

All but one of these technologies had two things in common – they do not utilize a standard-logic CMOS process flow and, more importantly, they are still in the development stage and not yet available for production silicon. The one exception – antifuse-based OTP.

Chip designers need to be aware of evolving technologies that they can use in future chip designs, but they also should consider new technologies that have already been silicon-proven. This includes new types of NVM memory, including highly scalable embedded OTP, which can overcome many of the limitations of traditional NVM technologies and thus reduce cost and improve chip performance.

Sidense OTP macros are available now, in production, and available in a wide variety of process nodes and foundries. Yes, traditional NVM technologies are running out of steam and, while emerging NVM technologies hold the promise of very dense, low power and, ultimately, cost-effective on-chip storage, chips cannot be built on promises.