The NVM Insider, Issue 5 - Page 3 - Outside Thoughts

Outside Thoughts:  Optimization Has Its Place ... But So Does Exploration

Adam Traidman, General Manager of Chip Planning Solutions, Cadence Design Systems

Traditional EDA flows, from synthesis through the backend, focus solidly on design optimization. From performance to timing, from power to area and, with the advent of the Design for Manufacturing paradigm, on through to yield, the mainstream EDA workhorse tools that have emerged over the past decade serve to optimize any given design to within nanometers of its life. The central idea behind the optimization-driven design methodology is to converge upon the most advantageous values for a specific metric or group of variables in order to achieve a set of pre-determined design goals.

Unfortunately, this optimization-driven flow assumes (correctly) that all of the toughest and most immutable decisions have already been made – the selection of IP (including processors, communication cores, NVM, and others), technology nodes, process variants, cell libraries, and so on. It follows that these choices have a profound and indelible impact upon both the technical integrity and the economic feasibility of a final chip design. What today’s designers need most, then, are new tools and methodologies at the system level to help explore their designs across these alternative implementation options, to assess and quantify the impact of each option. Designers must understand the interrelationships of these variables, and how they directly impact (and sometimes indirectly influence) key metrics such as area, power, leakage, yield and ultimately cost.

Call this process the architectural exploration stage of the design flow. While optimizing a design under a set of fixed boundary conditions – i.e.,with IP, technology node, process variant, and cell libraries already selected – still plays a vital role in the overall design process, it should be clear that designers would benefit immeasurably from an early and comprehensive exploration of how their key decisions will ultimately impact the technical and financial viability of the final chip.

The emergence of new technology nodes, such as those at 65nm and below, irrevocably altered the algebra of IC design. With these progressively smaller nodes came an explosion in the number of choices of IP and semiconductor process variants. A typical foundry that offers a simple ‘generic’ or ‘high speed’ process in the days of 180nm designs might offer half a dozen or more variants in 90nm or below. Attached to each of these variants, third-party IP vendors often offer numerous cell libraries and IP choices, each optimized for different effects, from leakage to performance to total power.

If the need for early architectural exploration increases with the rise in available process variants and cell libraries, then it certainly can be said that the need for exploration is equally a function of the degree of their technical and economic impact upon a final chip design. If, for example, the selection of one process node (or IP library) over another could be counted upon to produce a variance in the range of one to five percent, many design managers might opt out of early exploration, preferring instead to attempt to make up the difference with more optimization on the backend.

However, it has been amply demonstrated that the exploration-driven selection of process variants and cell libraries can produce variances up to an order of magnitude for certain pivotal effects such as leakage. The ability to capitalize upon such staggering variances is uniquely available only at the architectural exploration stage; these variances cannot be achieved through the optimization process, since the decision that might have illuminated them has long since been locked-in. Furthermore, from an economic perspective, non-recurring engineering (NRE) costs and other costs associated with implementation can, depending upon chip volumes, outweigh the technical merits of such alternative solutions.

Therefore, given that the number of process variants and IP options increases within smaller technology nodes, and that the selection of one over another can produce variances up to an order of magnitude for certain key effects, design teams clearly must spend more time early in the flow, using EDA tools designed specifically for the exploration of alternative implementation options. The current crop of EDA tools emphasizes optimization to the exclusion of nearly all else, and certainly optimization has earned an important place in the design flow. But today’s design teams need to put first things first by performing early architectural exploration to determine and quantify a design across various implementation options. Then, and only then, should they make use of the traditional tool flow to optimize a chip for production.