|The NVM Insider, Issue 8|
|Page 2 - Executive Opinion|
|Page 3 - Outside Thoughts|
|Page 4 - Sidense Out and About|
Sidense recently announced the availability of its ULP macros in TSMC's 180nm CMOS Logic process. With this announcement, Sidense reached another notable milestone - its newest NVM IP has reached TSMC's Minimum Acceptance Criteria (MAC). So what does this accomplishment mean to you?
In 2003 the VSI Alliance (VSIA) announced an initial version of the Quality IP Metric (QIP), developed over several years by many concerned companies including Freescale, Mentor Graphics, Synopsys, Cadence, Denali and many others. Companies and organizations throughout the world contributed to QIP and by 2007, Version 4.0 launched with much requested verification IP included. The reason for the interest in QIP then and now was an awareness of the need to evaluate semiconductor IP cores for suitability and also a desire to create reusable IP. The result of appropriately applying QIP is faster design times, reduced project risks, unplanned effort and silicon respins. These benefits can lead to significantly reduced design costs.