Support & Resources


Designing IP for Process Portability Maximizes Reuse

Article in by Jim Lipman, Marketing Director, Sidense

Abstract -   When evaluating IP attributes, IP integrators consider several parameters including cost, testability, availability of proven silicon, level of support and performance. However, one important consideration is often either ignored or assigned a low level of importance – portability between silicon foundries at the same process node. This is unfortunate, since maximizing IP reusability goes beyond reuse of that IP in different chips. Designers must also consider IP reuse at the same process node but at different foundries, particularly important for third-party IP providers, as well as potential future migration of the IP to other process nodes.  Read the complete story....

Tech Tip: Successful IP Equals Product plus Service

Article in by Jim Lipman, Marketing Director, Sidense,

Abstract -   Suppliers in various evolving segments of the semiconductor industry have learned, often painfully, that customer service goes hand-in-hand with a good product. This has certainly been true for EDA and ASIC vendors and now has become a key differentiator for silicon IP.  Read the complete story....

Foundry-Friendly Memory IP for Analog Trimming and Sensor Calibration

Jim Lipman, Marketing Director, Sidense

Integrating third-party silicon memory intellectual property (IP) is not simple. While IP integrators are looking for turnkey IP solutions, problems caused by foundry differences at the same process node, difficulties associated with process scalability, and variability of both fabrication processes and analog circuits and sensors make "foundry-friendly" memory IP design for mixed-signal chips difficult.

This article discusses the requirements for analog trimming and sensor conditioning mechanisms, and describes the architecture and technology of a reliable, embedded non-volatile memory (NVM) that minimizes dependence on foundry-specific process steps. The field programmable memory and support circuitry can be implemented in standard logic CMOS processes, is inherently scalable to leading edge process nodes, and is very tolerant of process variability - a key consideration below 90-nanometers. When implemented in silicon, memory macros based on this technology provide an efficient mechanism for in situ digital calibration of analog sensors, such as those encountered in automotive and industrial applications, and for trimming analog circuitry to increase silicon yield.

Read more: Foundry-Friendly Memory IP for Analog Trimming and Sensor Calibration

IEC Executive Perspectives DesignCon 2009 Xerxes Wania, President and CEO

Podcast on IEC  Executive Perspectives  DesignCon 2009  with Xerxes Wania, President and CEO, SIdense Corp.
Abstract - Sidense with Xerxes Wania, President and CEO.

IP Lightens Up

Article in New Electronics by Louise Joselyn,

Abstract -   Semiconductor IP is proving one of the few glimmers of light in a gloomy high tech market. Despite a slow start and a poor outlook in the early 1990s, the IP market has defeated its many sceptics and is enjoying significant annual growth.  Read the complete story....

Sidense Makes the List: EE Times Updates List of Emerging Startups

Article in EE Times by Peter Clarke,

Abstract -   The list of EE Times 60 Emerging Startups, first published in April 2004, has been updated to version 8.0, reflecting the latest corporate, commercial, technology and market conditions. Twenty-three companies have been brought onto the Silicon 60.  Read the complete story....

Up-And-Comers Threaten Flash Memory's Supremacy

Article in by Richard Quinnell,

Abstract -   As the decade closes, the major battleground in memory technology lies squarely with nonvolatile (NV) devices.   Read the complete story....

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