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Designing IP for Process Portability Maximizes Reuse

Article in ChipDesignMag.com by Jim Lipman, Marketing Director, Sidense

Abstract -   When evaluating IP attributes, IP integrators consider several parameters including cost, testability, availability of proven silicon, level of support and performance. However, one important consideration is often either ignored or assigned a low level of importance – portability between silicon foundries at the same process node. This is unfortunate, since maximizing IP reusability goes beyond reuse of that IP in different chips. Designers must also consider IP reuse at the same process node but at different foundries, particularly important for third-party IP providers, as well as potential future migration of the IP to other process nodes.  Read the complete story....

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