1. How long have you been in business?
10 Years – Sidense was founded in 2004
2. Where is Sidense based?
Company headquarters are in Ottawa, Ontario, Canada and we have regional sales offices worldwide.
3. How many customers and tape outs do you have? Have you proven volume production?
We have over 125 customers and Sidense OTP macros have been used in over 400 designs. We have proven volume production in many of these designs.
4. What are the key applications for OTP?
Sidense OTP is used for analog trimming and calibration, key storage, code storage, ID tags and chip and processor configuration. Customers are using our OTP in many applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial electronics.
5. What are your key selling points?
Key selling points of our patented, one-transistor one-time programmable (1T-OTP) memory are:
- Very small footprint (1T bit cell)
- Low active and standby power • Very portable between foundries
- Very scalable with process – available from 180nm to 20nm including BCD and HV nodes and we are developing 1T-OTP macros for FinFET architecture.
- Field programmable
- Very secure
- Highly reliable
6. Are there any masks or process adders?
No additional masks or process steps are required for a standard-logic CMOS process
7. Do you have to do wafer bake?
No wafer bake is required.
8. What is your retention rating?
Our OTP has a minimum retention time of 10 years at 125°C and full 100% read duty cycle.
9. What process nodes do you support?
We currently support 180nm to 20nm with many variants across these process nodes.
10. What if you don’t currently support my particular process node?
We need to talk to you about your product plans and potential customers to determine whether or not to port our OTP to the node in which you are interested.
11. What are typical program times?
Program times are dependent on process node, variant and array architecture. They can be as low as 50µs/bit with some OTP configurations offering multi-bit programming. Programming can be done at test, in-package or in the field with either an integrated charge pump of from an external source.
12. What are typical read access times?
Read access times are dependent on the OTP product, process node and read mode. They go down to 10ns.
13. How do you compare to other antifuse NVM?
Sidense OTP is based on a patented split-channel 1T bit-cell (1T-Fuse™) that is very portable, scalable, highly reliable, field-programmable and small.
14. How do you compare to floating gate?
Floating gate NVM is based on charge-storage. Sidense OTP is antifuse-based and bit cell contents do not depend on stored charge. The Sidense 1T bit cell is also much smaller than a comparable bit cell in a floating-gate NVM technology and is much more secure, since memory contents cannot be read by voltage or scanning techniques.
15. How does antifuse programming work?
The antifuse programming involves a permanent structural change. When the bit cell is subjected to the programming voltage, the thin gate oxide over the transistor channel melts locally and recrystallizes into silicon monocrystal, forming a conductive channel. Once programmed, a bit cell cannot be un-programmed. Unlike NVM using storage-based devices, the programmed bits in Sidense’s 1T-OTP bit cells cannot be reversed.
16. How do you compare to foundry fuses?
1T-OTP bit cells are smaller and much easier to program and read. 1T-OTP is also field-programmable.
17. What are your deliverables?
Deliverables include datasheets, application notes, integration guidelines, Verilog models, .lib file, .db file, LEF file, GDSII file and LVS netlist.
18. What is your business model?
The Sidense OTP business model follows a very typical industry standard hard IP licensing model comprising a license component plus royalty. There are several license variations available including single use, multi-use, unlimited-use and subscription. Support and maintenance are included for the first year.
19. Is there a royalty?
Yes – we have royalties associated with the licensing of our OTP macros
20. Is support and maintenance included?
Only for the first year of a license. Beyond that period there is an extra charge for annual support and maintenance.
21. How long does it typically take to integrate your IP?
Sidense provides a full Macro Integration kit (includes datasheets, application notes, integration guidelines, Verilog models, .lib file, .db file, LEF file, GDSII file and LVS netlist). Integration is relatively straightforward and requires no non-standard processing steps. The Sidense Applications team is always on-hand to help.
22. How can I get access to datasheets and application notes?
Datasheets and application notes can be downloaded from our website with registration and, for some information, an NDA in place.
23. How do I contact a local person in US West / US East / Europe / Japan / Taiwan / China?
Contact information is on the Sidense website at: http://www.sidense.com/contact/contact-sidense.html
24. Can I get a list of customer references?
Yes, at the appropriate stage of engagement and under NDA.
25. Can you do automotive grade?
Yes – we have products available for operation up to 150°C for automotive “under the hood” operation (AEC-Q100 Grade 0).
26. Is this field programmable?
Yes, either with an integrated charge pump or from an external source.
27. Does the IP include a charge pump, BIST, ECC?
This depends upon the macro chosen. Sidense OTPs are extremely flexible and can be supplied with or without IPS, BIST and ECC. The SHF (for advanced nodes) also has the additional option of interface circuitry available as a soft (RTL) macro.
28. What sort of visual & electrical security do you have?
The difference between a programmed and un-programmed antifuse cell is virtually impossible to detect using visual techniques (reverse-engineering, de-processing). Determining a cell’s content (0 or 1) via voltage or current scanning techniques is also almost impossible to determine, since the antifuse bit cell’s state does not depend on stored charge. An optional differential read mode eliminates power signatures, adding an extra level of security. On the macro level, there are additional features in place to increase security.
29. Minimum bit count available?
Product dependent and down to 16 bits
30. Maximum bit count available?
Product dependent and up to 1.28 Mbits
31. Does your split-channel architecture generate DRC violations? How do you address them?
Yes, but most memories do. We have no problem getting a waiver from every foundry and IDM we support