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FAQs

How long have you been in business?
Sidense was founded in 2004

Where is Sidense based?
Company headquarters are in Ottawa, Ontario, Canada and we have regional sales offices worldwide

How many customers do you have? Have you proven volume production?
We have over 170 customers and Sidense 1T-NVM macros have been used in over 670 designs. We have proven volume production in many of these designs, in a wide range of processes and process variants.

What are the key applications for 1T-NVM?
Based on its patented split-channel 1T-Fuse™ bit cell, Sidense 1T-NVM is used for analog trimming and calibration, key storage, code storage, ID tags and chip and processor configuration. Customers are using our 1T-NVM macros in many applications ranging from mobile and consumer devices to high-temperature, high-reliability automotive and industrial systems.

What are your key selling points?
Key selling points of our patented, one-transistor one-time programmable (1T-OTP) memory are:

  • Very small footprint (1T bit cell)
  • Low active and standby power
  • Very portable between foundries
  • Very scalable with process – available from 180nm to 16nm, including SOI, FD-SOI, BCD, HV, and other specialty nodes and FinFET architectures. We are developing 1T-NVM for FinFETs below 16nm as well
  • Field programmable
  • Very secure
  • Highly reliable

Are there any masks or process adders?
No additional masks or process steps are required for a standard-logic CMOS process

Do you have to do wafer bake?
No wafer bake is required.

What is your retention rating?
All our 1T-NVM has a minimum retention time of 10 years at 125°C C (AEC-Q100 Grade 1) and full 100% read duty cycle. We also have 1T-NVM products available for selected BCD processes that have a minimum retention time of 10 years at 150°C (AEC-Q100 Grade 0) and full 100% read duty cycle.

What process nodes do you support?
We currently support 180nm to 16nm with many variants across these process nodes.

What if you don’t currently support my particular foundry or process node?
We need to talk to you about your product plans and potential customers to determine whether or not to port our 1T-NVM to the node in which you are interested.

What are typical program times?
Program times are dependent on process node, variant and array architecture. They can be as low as 50µs/bit with some 1T-NVM configurations offering multi-bit programming. Programming can be done at test, in-package or in the field with either an integrated charge pump or from an external source.

What are typical read access times?
Read access times are dependent on the 1T-NVM product, process node and read mode. They go down to 10ns.

How do you compare to other antifuse NVM?
Sidense 1T-NVM is based on a patented split-channel 1T bit-cell (1T-Fuse™) that is very portable, scalable, highly reliable, field-programmable and small.

How do you compare to floating gate?
Floating gate NVM is based on charge-storage. Sidense 1T-NVM is antifuse-based and bit cell contents do not depend on stored charge. The Sidense 1T bit cell is also much smaller than a comparable bit cell in a floating-gate NVM technology and is much more secure, since memory contents cannot be read by voltage or scanning techniques.

How does antifuse programming work?
The reliable antifuse programming involves a permanent structural change. When the bit cell is subjected to the programming voltage, the thin gate oxide over the transistor channel melts locally and recrystallizes into silicon monocrystal, forming a conductive channel. Once programmed, a bit cell cannot be unprogrammed. Unlike NVM using storage-based devices, the programmed bits in Sidense’s 1T-NVM bit cells cannot be reversed.

How do you compare to foundry fuses?
1T-NVM bit cells are smaller, more easily scaled to smaller process nodes and much easier to program and read. 1T-NVM is also field-programmable.

What are your deliverables?
Deliverables include datasheets, application notes, integration guidelines, Verilog models, .lib file, .db file, LEF file, GDSII file and LVS netlist.

What is your business model?
The Sidense business model follows a very typical industry standard hard IP licensing model comprising a license component plus royalty. There are several license variations available including single use, multi-use, unlimited-use and subscription. Support and maintenance are included for the first year.

Is there a royalty?
Yes – we have royalties associated with the licensing of our 1T-NVM macros

Is support and maintenance included?
Only for the first year of a license. Beyond that period there is an extra charge for annual support and maintenance.

How long does it typically take to integrate your IP?
Sidense provides a full Macro Integration kit (includes datasheets, application notes, integration guidelines, Verilog models, .lib file, .db file, LEF file, GDSII file and LVS netlist). Integration is relatively straightforward and requires no non-standard processing steps. The Sidense Applications team is always on-hand to help.

How can I get access to datasheets and application notes?
Datasheets and application notes can be downloaded from our website with registration and, for some information, an NDA in place.

How do I contact a local person in US West / US East / Europe / Japan / Taiwan / China?
Contact information is on the Sidense website

Can I get a list of customer references?
Yes, at the appropriate stage of engagement and under NDA.

Can you do automotive grade?
Yes – As a minimum most products are qualified to 125°C (AEC-Q100 grade 1) and some BCD designs are qualified for operation at 150°C for automotive “under the hood” operation (AEC-Q100 Grade 0).

Are Sidense 1T-NVMs field programmable?
Yes, Sidense provides Integrated Power Supply (IPS) module that includes a charge pump to generate the required programming voltage.

Does the IP include BIST, ECC etc. ?
This depends upon the macro chosen. Sidense 1T-NVM macros are extremely flexible. The SHF (for advanced nodes) includes a controller block that takes care of BIST, ECC, and the programming algorithm. This is supplied a soft (RTL) macro.

What sort of visual & electrical security do you have?
The difference between a programmed and unprogrammed antifuse cell is virtually impossible to detect using visual techniques (reverse-engineering, de-processing). Determining a cell’s content (0 or 1) via voltage or current scanning techniques is also almost impossible to determine, since the antifuse bit cell’s state does not depend on stored charge. An optional differential read mode eliminates power signatures, adding an extra level of security. On the macro level, there are additional features in place to increase security.

Minimum bit count available?
Product dependent and down to 16 bits

Maximum bit count available?
Product dependent and up to 1.28 Mbits

Does your split-channel architecture generate DRC violations? How do you address them?
Yes, but most memories do. We have no problem getting a waiver from every foundry and IDM we support

Are you IS0-9001 certified?
Yes – Sidense is proud to be certified, by BSI,  to  the latest ISO-9001 standard (2015)

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