A quarterly look at embedded NVM/OTP happenings
Executive Opinion: Quality, Reliability, and TSMC's IP9000
Todd Humes, VP of Product Engineering and Jim Lipman, Director of Marketing, Sidense
Sidense recently announced the availability of its ULP macros in TSMC's 180nm CMOS Logic process. With this announcement, Sidense reached another notable milestone - its newest NVM IP has reached TSMC's Minimum Acceptance Criteria (MAC). So what does this accomplishment mean to you?
Outside Thoughts: IEEE Work on Ensuring Quality Continues
By Kathy Werner, Chair, IEEE P1734 Quality IP Workgroup
In 2003 the VSI Alliance (VSIA) announced an initial version of the Quality IP Metric (QIP), developed over several years by many concerned companies including Freescale, Mentor Graphics, Synopsys, Cadence, Denali and many others. Companies and organizations throughout the world contributed to QIP and by 2007, Version 4.0 launched with much requested verification IP included. The reason for the interest in QIP then and now was an awareness of the need to evaluate semiconductor IP cores for suitability and also a desire to create reusable IP. The result of appropriately applying QIP is faster design times, reduced project risks, unplanned effort and silicon respins. These benefits can lead to significantly reduced design costs.
Sidense Out and About
- Secure Sidense OTP Helps Parade Provide Protected Video Content
- Sidense Raises $5 million in Venture Capital to Expand Product Development
- Sidense Corp. Reacts to Kilopass Allegations
- Sidense to Prove Kilopass Patent Invalid
- Sidense Introduces ULP OTP Memory for eFuse Replacement
Sidense Authored Articles
- Dispelling the Myths Surrounding Antifuse OTP. Upcoming June 15 in ChipEstimate.com's IP Connections newsletter
Upcoming Conferences/Tradeshows of Interest
- TSMC Technology Symposium in Herzelia, Taiwan and Yokohama:
- Herzelia, Israel, June 14, 2010
- Hsin Chu, Taiwan R.O.C., June 24, 2010
- Yokohama, Japan, July 2, 2010
- Design Automation Conference 2010
Anaheim, CA (June 14-16, 2010).
Join Sidense at the Design Automation Conference at the ChipEstimate.com booth (#521), Monday-Wednesday, June 14-16, 2010, in Anaheim, California. We will also be exhibiting in the GLOBALFOUNDRIES partners' booth (#275) throughout exhibit hours and making presentations on Monday and Wednesday.
Find our IP catalog on ChipEstimate.com.
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