A quarterly look at embedded NVM/OTP happenings
Xerxes Wania, President and CEO, Sidense
I want to welcome you to the premier issue of Sidense’s e-Newsletter, “The NVM Insider.” In each issue, you will find interesting columns, pointers to key industry news concerning embedded non-volatile memory, a summary of Sidense’s accomplishments over the preceding quarter and a question we hope you will answer that will help us understand your views regarding this rapidly growing segment of the microelectronics industry.
Rich Wawrzyniak, Senior Analyst ASICs and SoC, Semico
One of the underlying facts of the current System-on-a-Chip (SoC) market is that the use of embedded memory, in all its different variations, is growing. There is not a single SoC in the market today that does not employ some form of embedded memory at some density level whether it is for main memory, data cache, security or other uses. In fact, the ITRS roadmap from 2005 shows the die area given over to embedded memory content for the typical SoC reaching approximately 94% by 2014.
NVM on the Mind
Notes from ESC Sidense: OTP memory IP slipping between the stereotypes
Ron Wilson’s Blog, EDN (April 15, 2008)
If you ask system designers today about one-time-programmable memory, they tend to think either of large, mask-programmed chips used for code storage, or of tiny amounts—bits or bytes--of embedded OTP used to store ID numbers, encryption keys, or trimming data on chips. But there is at least one version of OTP that fits in between those two concepts, and for that reason may not get the recognition it deserves: relatively dense, low-power OTP memory IP intended to be embedded on SoCs for execute-in-place code storage, or storage of large parameter tables.
Read more: EDN (April 15, 2008)
NV memory beyond floating gate – NV memory innovators
Richard Quinnell, EE Times (May 20, 2008)
Many applications need to archive data or retain system information after power-down. These tasks fall to nonvolatile memory that must be in-circuit writable at least once, and often many times. Floating-gate data storage, the traditional technology used to create such NV memory, faces increasing challenges as process lithography shrinks, prompting evolving new technologies to take over.
Read more: EE Times
More from DAC: Can IP assembly ever be a real methodology for SoC design?
Ron Wilson’s Blog, EDN (June 16, 2008)
Some of the interesting action at DAC is always in the vendor-sponsored events in the surrounding hotels. One example this year was a panel, sponsored by memory IP vendor Sidense and recent Cadence acquisition ChipEstimate, on the future of IP integration methodology. The question before the panel was whether today's practice of searching out, qualifying, and integrating third-party IP could ever have the rigor and consistency to be a methodology, or if it would always remain a case-by-case scramble.
Read more: EDN (June 16, 2008)
- Next >>