Support & Resources

The NVM Insider, Issue 6

December 2009

A quarterly look at embedded NVM/OTP happenings


Proudly released in partnership with
This newsletter is released in partnership with ChipEstimate
Find our IP catalog on ChipEstimate.com.


Placeholder

Tech Tidbits: Converting Sidense OTP to Mask Programmable ROM

Todd Humes, VP of Product Engineering and Jim Lipman, Director of Marketing, Sidense

For large amounts of on-chip code and data, mask ROM provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field, either to correct errors or to provide updated storage, which can lead to expensive silicon re-spins and time-to-product delays.

Read more

Tomasz Wojcicki, VP of Engineering, Sidense

Executive Opinion: Successful Memory IP Development Depends on GEP

Tomasz Wojcicki, VP of Engineering, Sidense

Through years of experience, people develop ‘their’ ways of doing things. With time they become ‘their own’ best engineering practices. Some of these are captured in writing and become part of a Good Engineering Practice (GEP). Some never leave the stage of ‘my’ best engineering practice.

Read more

Outside Thoughts: The Importance of Specialized Memory Markets: Embedded NVM and OTP

Bob Merritt and Sherry L. Garber, Convergent Semiconductors

The forecast for the memory market always appears to center around a move to a universal memory that will replace all of the other memory types in the marketplace. This might be possible if end applications would quit expanding the range of memory performance attributes. Instead what is happening is a demand for a greater variety of memory types. One of those is Non-Volatile Memory (NVM), with demand that is growing exponentially as mobile devices with lower cost requirements proliferate. One of the stars is embedded NVM.

Read more

Placeholder

Customer Corner: WHDI – The New Standard for Wireless Whole Home Uncompressed HD

AMIMON uses OTP memory in implementing the WHDI security layer
Noam Geri, VP Marketing & Business Development, AMIMON Inc.

Wireless Home Digital Interface™ (WHDI™) is the new wireless High-Definition video standard that will change the way people use Audio/Video devices in the home. WHDI is the first and only standard that enables top-quality wireless uncompressed HD video delivery throughout the home, allowing consumers to connect any source in the home to any display.

Read more

Sidense Out and About

Press Releases

Editorial Coverage

NVM on the Mind

Recent Articles

 


Tech Tidbits

Tech Tidbits: Converting Sidense OTP to Mask Programmable ROM

Todd Humes, VP of Product Engineering and Jim Lipman, Director of Marketing, Sidense

For large amounts of on-chip code and data, mask ROM provides an inexpensive and easily programmed storage mechanism. However, the inability to configure ROM after wafer processing means that information stored in the ROM cannot be changed in the field, either to correct errors or to provide updated storage, which can lead to expensive silicon re-spins and time-to-product delays.

This is why you should consider using Sidense OTP for your silicon development and prototyping. There are several reasons why field-programmable OTP makes sense:

  • You can commit to silicon before your code is finalized, which will accelerate your time-to-product
  • You have the flexibility of trying different versions of your chip’s code
  • Your chip can support additional features that may not be available on initial silicon
  • Sidense OTP is very dense and has fast access times
  • The conversion to mask ROM for cost reduction is easy to achieve

Using Sidense OTP in place of ROM does require slightly more area. In addition, the programming time Sidense OTP requires increases approximately linearly with bit count. Since ROM is programmed during chip fabrication, there is no programming time or cost at test. While these considerations are not very important for small bit count applications, they are at high bit counts, for example, when the OTP is storing hundreds of thousands of bits of boot code or firmware. Verifying Sidense OTP also results in additional test time.

These OTP factors are acceptable at a prototype phase of chip development, but may become too expensive during production, especially for high bit-count applications. However, the ability to complete code development during silicon fabrication and make and test code changes during prototyping coupled with the ability to accelerate market entry and reduce final product cost is a compelling argument for using field-programmable OTP during product development.

You can reduce programming time for SiPROM macros by programming one bit per bank simultaneously instead of a single bit at a time. This reduces programming time by a factor of two or four, depending on the number of banks in the macro configuration you are using. However, converting all or part of your OTP macro to mask ROM can significantly reduce overall programming time along with ATE test cost.

Conversion to mask ROM requires a single GDS layer change – diffusion (thin gate oxide) – within a standard process flow. Since many customers do their prototype development using a non-critical (and less expensive) mask set, when they go into production they will be purchasing a production quality mask set anyway, so they do not incur any incremental costs of this layer change. If a customer uses a dedicated prototype mask set to accelerate product time to market, the cost of changing this layer is easily justified.

Conversion to mask ROM

There are many benefits of converting either all or part of a Sidense OTP macro to mask ROM once all or part of the bit storage is frozen.

  • Significant cost savings due to the reduced time for ATE programming of the macro. For differential or redundant read-mode macro operation, the programming time savings is even greater than for single-cell read mode
  • Since the memory footprint does not change when converting field-programmable OTP to mask ROM, NRE costs for layout are minimal
  • You can “mix and match” OTP and ROM in the same macro for applications such as factory or field trimming of analog circuitry and sensor conditioning; product customization (one silicon chip with several variants) where functionality is enabled by OTP programming; chip identification, lot date coding, and other ID functions; future code patching; and end customer personalization, such as that required for digital hearing aids.

The following example shows a 128 Kbit (8K x 16) Sidense OTP macro used for storing code. 112 Kbits of code storage have been finalized and the macro section with this stored code converted to ROM. After the conversion, the programming time for this macro is reduced by 87.5%.

example showing a 128 Kbit Sidense OTP macro used for storing code

Contact This email address is being protected from spambots. You need JavaScript enabled to view it. for more details on implementing ROM in your design.

 


Tomasz Wojcicki, VP of Engineering, Sidense

Executive Opinion: Successful Memory IP Development Depends
on GEP

Tomasz Wojcicki, VP of Engineering, Sidense

Through years of experience, people develop ‘their’ ways of doing things. With time they become ‘their own’ best engineering practices. Some of these are captured in writing and become part of a Good Engineering Practice (GEP). Some never leave the stage of ‘my’ best engineering practice.

By the nature of things, startups tend to be less formal. Processes, methodologies, and check-off lists are introduced as the company matures and its customer base grows. It is quite likely that a fair amount of GEP originated from live experiences, good or bad.

It is hard to argue that a good, detailed specification is one of the most important pieces of a GEP. Whether it is an external specification or a description to be used between functional groups in the organization, a good spec will directly impact whether the project or product is done on time, effectively, and will meet customer/company expectations, or it will lead to costly schedule overruns, missed delivery dates, and repeated silicon runs.

Memory is quite unique amongst silicon IP. The number of possible memory configurations makes it almost impossible to simulate and characterize all of them. Each memory company develops its own way of dealing with this challenge. Some use tools and brute force and computational power of modern computers, while others develop sophisticated circuit optimization and minimization techniques. Either way, a tested, proven, accurate and a fast methodology to simulate any memory configuration is a key component of GEP.

Close cooperation of circuit and layout engineers is critical for area-efficient designs. It is not far from the truth that layout is leading the design effort. Quite frequently circuit solutions are dictated by layout constraints.

Good simulation techniques and thorough circuit and layout reviews, along with functional verification with comprehensive test benches should yield working and well performing IP but nothing replaces a test chip. Having the IP manufactured at least once will provide a lot of insight into how a memory macro will work in customer applications. Corner lots provide even more valuable information about operating ranges and available margins. Obviously the most detailed testing will not help if the results are not fed back to the design group.

All what has been mentioned so far is quite generic and broad. These fundamental pieces of a GEP have to be supported by many ‘smaller ticket’ items such as good project documentation, a clean and easy to understand set of schematics, a design changes tracking system and… it never hurts to work with a team of engineers with their own good engineering habits.

 

 


Outside Thoughts:  The Importance of Specialized Memory Markets: Embedded NVM and OTP

Bob Merritt and Sherry L. Garber, Convergent Semiconductors

The forecast for the memory market always appears to center around a move to a universal memory that will replace all of the other memory types in the marketplace. This might be possible if end applications would quit expanding the range of memory performance attributes. Instead what is happening is a demand for a greater variety of memory types. One of those is Non-Volatile Memory (NVM), with demand that is growing exponentially as mobile devices with lower cost requirements proliferate. One of the stars is embedded NVM.

Current memory technologies support a value ratio between the processor and the memory that is heavily biased toward the processor.  This separation is essentially propagated by the fact that existing processes for high-performance memory and high-performance logic are incompatible.  With many new applications, higher performance processing and larger memory sizes are no longer the requirements.

Yet new and emerging memory technologies continue to focus on high-performance embedded NVM due to the potential process compatibilities.  The objective of these development programs is that for those applications for which the processing requirements are small enough, the memory performance attributes of density, speed, and non-volatility begin to contribute more and more of consumer's perceived value of the OEM's end product.  Ultimately this trend toward embedding high performance NVM in the same process with the processor will shift that value proposition toward the memory in many common applications with relatively simple processing requirements.  An example of this is that the relatively low performance of today’s Netbook processors is eroding demand from Laptops; processor suppliers are beginning to compete on cost, in other words manufacturing efficiencies, which had typically been the forte of memory technologies. 

Under the market conditions being supported by mobile personal computing devices, as the competitive value of the end product begins to focus more on the mobility and less on data processing, Moore's Law begins to assume a different impact on the value ratio between the various technologies.  Moore's Law suggests that in these highly mobile applications residing somewhere between cell phones and performance-oriented laptops, the single processor element becomes the commodity—the perceived value of the memory increases relative to the total user experience in terms of communications and stored entertainment-oriented capabilities.  Furthermore, once this ratio between the memory and the processing element begins to shift in the direction of the memory technologies, that point of transition in the value ratio between the memory performance attribute and the processor shifts upward in performance at a rate doubling every two years as predicted by Moore's Law. 

The decline of the desktop PC architecture as the primary target application for development of new memory technologies continues to increase the emphasis on other memory performance attributes. Trends in memory usage are providing a much richer selection of memory options and characteristics; a quick check with Micron’s website already shows over 1,128 different DRAM configurations separated into 23 distinct product groups.

However, it has been amply demonstrated that the exploration-driven selection of process variants and cell libraries can produce variances up to an order of magnitude for certain pivotal effects such as leakage. The ability to capitalize upon such staggering variances is uniquely available only at the architectural exploration stage; these variances cannot be achieved through the optimization process, since the decision that might have illuminated them has long since been locked-in. Furthermore, from an economic perspective, non-recurring engineering (NRE) costs and other costs associated with implementation can, depending upon chip volumes, outweigh the technical merits of such alternative solutions.

The demand for a wider selection of non-volatile memory technologies is likewise increasing at a rapid rate as we shift toward more mobile and customer-specific applications. The requirements for field programmability and customer-specific hardware customization of OEM products are continuing to accelerate.

The Sidense 1T-Fuse™ Logic NVM can be manufactured on standard logic CMOS process, requires no additional mask layers or process steps, and can be programmed in the field as well as during wafer or production testing. We believe that the market demand for such performance attributes is in the mainstream of memory applications, and that demand will continue to grow.

You can contact Bob and Sherry at Convergent Semiconductors:

Bob Merritt
This email address is being protected from spambots. You need JavaScript enabled to view it.
949-488-7961

Sherry Garber
This email address is being protected from spambots. You need JavaScript enabled to view it.
480-377-8020

 

 


Customer Corner

Customer Corner:  WHDI – The New Standard for Wireless Whole Home Uncompressed HD

AMIMON uses OTP memory in implementing the WHDI security layer

Noam Geri, VP Marketing & Business Development, AMIMON Inc.

Wireless Home Digital Interface™ (WHDI™) is the new wireless High-Definition video standard that will change the way people use Audio/Video devices in the home. WHDI is the first and only standard that enables top-quality wireless uncompressed HD video delivery throughout the home, allowing consumers to connect any source in the home to any display.

WHDI is based on a revolutionary video-modem technology operating in the 5GHz unlicensed band in which the wireless transmission is optimized for video delivery. Uncompressed HD streams up to 1080p/60Hz with deep color can be transmitted wirelessly through walls, and with a range of over 30 meters.

WHDI can enable a wireless link between HDTVs and sources such as set-top-boxes, DVD players, gaming consoles and computers. WHDI is also ideally suited for enabling a wireless uncompressed HD connection between TVs and portable devices such as notebook PCs, netbooks and even smart-phones and portable media players. As more and more content is being accessed via the Internet and decoded on PCs, WHDI enables consumers to view this content also on a large screen TV.

WHDI uses Hollywood approved HDCP 2.0 for copy protection and defines an additional WHDI security layer for access control and privacy. The HDCP 2.0 copy protection protocol, which is controlled by DCP LLC, protects the rights of the content owners by preventing copying of the content delivered over the wireless link. HDCP 2.0 uses an RSA key exchange algorithm to establish an encrypted link and requires robust and secure storage of the HDCP keys. AMIMON uses OTP memory in its WHDI semiconductor components to store these keys.

The WHDI security layer is an additional security layer that is intended to prevent unauthorized access to the WHDI home network and ensures the privacy of the wireless transmissions. The WHDI security layer is based on a home domain method in which users will register new WHDI devices into their WHDI home domain. All devices within the home domain are authorized to communicate with each other. The WHDI security layer relies on RSA keys for encryption and certification and these keys are also stored on the WHDI ICs using OTP.

Pre-WHDI standard products based on WHDI’s video modem technology have been in the market since 2008, including wireless HDTVs and accessories by leading TV manufacturers as well professional and medical system manufacturers. The WHDI specification is now available to adopters and WHDI modules by multiple module makers are available now, enabling interoperable WHDI products to be available to consumers in 2010.

For more information please visit www.amimon.com or www.whdi.org or email: This email address is being protected from spambots. You need JavaScript enabled to view it.

 


Sidense Out and About

Press Releases

Editorial Coverage

NVM on the Mind

Recent Articles

If you would like to read more, go to: The NVM Insider Archives