Sidense's patented  1T-Fuse™ Logic NVM IP is an antifuse-based, embedded one-time programmable (OTP) technology that is secure, reliable, low power and cost-effective. The IP can be manufactured in standard-logic CMOS processes and does not require any additional mask layers or process steps.

Sidense Patented 1T-Fuse Split Channel Bit CellSidense 1T-Fuse™ technology is based on a one-transistor non-volatile memory cell that does not rely on charge storage, rendering a secure cell that is extremely difficult to reverse engineer. The 1T-Fuse™ is smaller than alternative NVM IP manufactured in a standard-logic CMOS process. The OTP can be programmed in the field or during wafer or production testing.

Sidense products are available from 180nm to 20nm and are portable to smaller geometries. Supported foundries are TSMC, UMC, Fujitsu Microelectronics Limited (FML), SMIC, TowerJazz, IMagnaChip,GLOBALFOUNDRIES and ON Semiconductor.

Patented Split-Channel Cell

The 1T-Fuse™ bit cell is a two-terminal, split-channel device that looks like an MOS capacitor in the un-programmed state and a diode-connected MOS transistor in the programmed state. All programming occurs in the transistor's channel region for high reliability and repeatability.

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